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Abstract            Volume:4  Issue-3  Year-2016         Original Research Articles

Online ISSN : 2347 - 3215
Issues : 12 per year
Publisher : Excellent Publishers
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CAN Controller Modelling and Simulation for its Implementation in FPGA (SoC) using Verilog for Integrated CAN Node
Duhita B. Paratane* and A.M.Patil
M.E. Electronics and Telecommunication, J. T. Mahajan College of Engineering, Faizpur, India
*Corresponding author

A CAN (Controller Area Network) node typically consist of a CAN controller, the microcontroller and CAN transceiver. This system requires the microcontroller containing a CAN controller in it and a separate transceiver. Microcontroller integrated with CAN controller suffers performance penalty as it has to read input gives output to actuators along with CAN message reception processing and communication. All these tasks are done in microcontroller in sequential manner as per standard software application. Also we cannot use a general microprocessor for controlling the CAN network system, since we required a system built around the standalone controllers which is bulky and not cost effective. To resolve this problem, this paper presents Verilog implementation of a CAN controller in Altera Cyclone V SoC (FPGA) with Cortex A9 microprocessor for controlling CAN network. This facilitates implementation of multiple CAN controller in one device with configurable priorities. Also avails highest possible speed of controller due to parallel processing of data in FPGA. In this paper a CAN controller RTL (Register Transfer Level) logic is implemented using Verilog in accordance with CAN protocol (version 2.0A and 2.0B). Each and every functional modules of CAN controller is simulated and verified. This controller connected via Avalon Memory mapped interface, with the Hard Processor (HPS) present in Cyclone V SoC for achieving data transfer control. Complete implementation of CAN node is synthesized into Altera’s Cyclone V SoC using Quartus-II software.

Keywords: CAN (Controller area Network) controller, CAN node, FPGA, SoC, HPS, Verilog, Modules
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How to cite this article:

Duhita B. Paratane and A.M. Patil. 2016. CAN Controller Modelling and Simulation for its Implementation in FPGA (SoC) using Verilog for Integrated CAN Node.Int.J.Curr.Res.Aca.Rev. 4(3): 76-85
doi: http://dx.doi.org/10.20546/ijcrar.2016.403.009
Copyright: This is an Open Access article distributed under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike license.